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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20901-1e fujitsu semiconductor data sheet page mode flash memory cmos 128m (8m 16/4m 32) bit mbm29xl12df -70/80 n description the mbm29xl12df is 128m-bit, 3.0 v-only page mode and dual operation flash memory organized as 8m words by 16 bits or 4m words by 32 bits. the device is offered in 90-pin ssop and 96-ball fbga packages. this device is designed to be programmed in-system with the standard system 3.0 v vcc supply. 12.0 v vpp and 5.0 v vcc are not required for program or erase operations. the device can also be reprogrammed in standard eprom programmers. (continued) n product lineup n packages part no. mbm29xl12df ordering part number suffix 70 80 v cc (v) 3.0 to 3.6 2.7 to 3.1 max random address access time (ns) 70 80 max page address access time (ns) 25 30 max ce access time (ns) 70 80 max oe access time (ns) 25 30 90-pin plastic ssop 96-ball plastic fbga (fpt-90p-m01) (bga-96p-m02)
mbm29xl12df -70/80 2 (continued) the device provides truly high performance non-volatile flash memory solution. the device offers fast page access times of 25 ns and 30 ns with random access times of 70 ns and 80 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the page size is 8 words or 4 double words. the dual operation function provides simultaneous operation by dividing the memory space into four banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state- machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the program and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program tm algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each 32k words sector can be programmed and verified in about 0.3 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase tm algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 0.5 seconds. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits program and erase operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the words are programmed one word at a time using the eprom programming mechanism of hot electron injection.
mbm29xl12df -70/80 3 n features ? 0.17 m m m m m process technology ? single 3.0 v read, program and erase minimized system level power requirements ? simultaneous read/write (program and erase) operations (dual bank) ? flexbank tm * 1 bank a: 16 mbit (4k words 8 and 32k words 31) bank b: 48 mbit (32k words 96) bank c: 48 mbit (32k words 96) bank d: 16 mbit (4k words 8 and 32k words 31) ? high performance page mode 25 ns maximum page access time at v cc = 3.0 v to 3.6 v(70 ns random access time) 30 ns maximum page access time at v cc = 2.7 v to 3.1 v(80 ns random access time) ? 8 words page ( 16) / 4 double words page ( 32) size ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 90-pin ssop (package suffix : pfv) 96-ball fbga (package suffix : pbt) ? minimum 100,000 program/erase cycles ? sector erase architecture eight 4k words, two hundred fifty -four 32k words, and eight 4k words sectors any combination of sectors can be concurrently erased. also supports full chip erase ? dual boot block 16 by 4k words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range ? hiddenrom region 128 words of hiddenrom region by using device address of word mode 000000h to 00007fh (double word mode: 000000h to 00003fh) accessible through a hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? write protect pin (wp ) write protect ( wp ) function allows protection of outermost 2 4k words on both ends of boot sectors, regardless of sector protection/unprotection status ? accelerate pin (acc) at v acc , increases program performance ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically programs and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready / busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, the device automatically switches itself to low power mode. ? low v cc write inhibit v lko (continued)
mbm29xl12df -70/80 4 (continued) ? program suspend / resume suspends the program operation to allow a read in another word ? erase suspend / resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? in accordance with cfi ( c ommon f lash memory i nterface ) ? hardware reset pin (reset ) hardware method to reset the device for reading array data ? new sector protection persistent sector protection password sector protection ? hardware sector group protection hardware method disables any combination of sectors from program or erase operation *1: flexbank tm is a trademark of fujitsu limited, japan. *2: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29xl12df -70/80 5 n pin assignments (continued) ssop (top view) (fpt-90p-m01) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 n.c. n.c. acc wp we n.c. a 21 a 20 dw/w oe ce vss dq 31 /a -1 dq 15 dq 30 dq 14 vss v cc dq 29 dq 13 dq 28 dq 12 dq 27 dq 11 dq 26 dq 10 vss v cc dq 25 dq 9 dq 24 dq 8 v cc a 19 a 18 a 17 a 16 a 15 a 14 a 13 n.c. n.c. n.c. n.c. n.c. 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 n.c. n.c. n.c. reset ry/by a 0 a 1 a 2 a 3 a 4 a 5 v cc dq 0 dq 16 dq 1 dq 17 vss v cc dq 2 dq 18 dq 3 dq 19 dq 4 dq 20 dq 5 dq 21 vss v cc dq 6 dq 22 dq 7 dq 23 vss a 6 a 7 a 8 a 9 a 10 a 11 a 12 n.c. n.c. n.c. n.c. n.c.
mbm29xl12df -70/80 6 (continued) e10 dq 30 f10 v cc g10 dq 13 h10 dq 12 j10 dq 27 k10 dq 26 l10 v cc m10 dq 9 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. d9 e9 m9 l9 k9 j9 h9 g9 f9 n9 ce v ss v cc dq 24 v ss dq 11 dq 28 dq 29 dq 15 a 19 d8 e8 m8 l8 k8 j8 h8 g8 f8 n8 a 20 dw/w a 17 a 18 dq 25 dq 10 v ss dq 14 oe a 16 d7 e7 m7 l7 k7 j7 h7 g7 f7 n7 we n.c. a 14 a 15 dq 8 n.c. n.c. dq 31 /a -1 a 21 a 13 d6 e6 m6 l6 k6 j6 h6 g6 f6 n6 reset acc n.c. n.c. n.c. n.c. n.c. ry/by wp n.c. d5 e5 m5 l5 k5 j5 h5 g5 f5 n5 a 1 a 2 a 9 a 11 a 12 n.c. dq 2 a 0 a 3 a 10 d4 e4 m4 l4 k4 j4 h4 g4 f4 n4 a 4 a 5 a 6 a 8 dq 21 dq 5 dq 18 dq 16 dq 0 a 7 e3 m3 l3 k3 j3 h3 g3 f3 n3 v cc dq 23 dq 7 dq 6 dq 4 dq 19 v ss dq 1 v ss m2 l2 k2 j2 h2 g2 f2 dq 22 v cc v ss dq 20 dq 3 v cc dq 17 a11 b11 c11 p11 q11 r11 a1 b1 c1 p1 q1 r1 fbga (top view) marking side (bga-96p-m02)
mbm29xl12df -70/80 7 n pin descriptions mbm29xl12df pin configuration pin function a 21 to a 0 , a -1 address inputs dq 31 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable reset hardware reset / temporary sector group unprotection ry/by ready/busy output dw / w selects 32-bit or 16-bit mode wp hardware write protection acc program acceleration n.c. pin not connected internally v ss device ground v cc device power supply
mbm29xl12df -70/80 8 n block diagram n logic symbol v cc a 21 to a 0, a -1 reset we ce oe acc dq 15 to dq 0 dq 31 to dq 0 bank a address bank c address bank b address bank d address state control & command register status ry/by control cell matrix 16 mbit (bank a) x-decoder y-gating cell matrix 16 mbit (bank d) x-decoder y-gating cell matrix 48 mbit (bank b) x-decoder y-gating cell matrix 48 mbit (bank c) x-decoder y-gating v ss wp dw/w a 21 to a 0 oe ce reset dq 31 to dq 0 32 or 16 dw/w we ry/by 22 wp acc a- 1
mbm29xl12df -70/80 9 n device bus operation legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see " n dc characteristics" for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see "mbm29xl12df command definitions table". *2 : refer to section on "sector group protection". *3 : we can be v il if oe is v il , oe at v ih initiates the program and erase operations. *4 : v cc = 3.0 v to 3.6 v for 70 ns random access time v cc = 2.7 v to 3.1 v for 80 ns random access time *5 : protects outermost 2 4k words on both end of the boot block sectors. (sa0, sa1, sa268, and sa269) *6 : also used for "extended sector group protection". *7 : dq 30 to dq 16 = x (v il or v ih ) mbm29xl12df user bus operations table (dw/w = v il ) operation ce oe we wp dq 31 /a -1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 dq 15 to dq 0 * 7 reset autoselect manufacturer code * 1 l lhx l llllxxlv id code h autoselect device code * 1 llhx l hlllxxlv id code h extended autoselect device code * 1 l l h x l lhhhxx lv id code h l l h x l hhhhxx lv id code h read * 3 llhxa -1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 d out h standby h x x x x x x x x x x x x high-z h output disable l hh x x xxxxxxxxhigh-z h write (program/erase) l h l x a -1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 d in h enable sector group protection * 2, * 4 lv id x l lhlhhhlv id xh verify sector group protection * 2, * 4 l l hh l lhlhhhlv id code h boot block sector write protection * 5 x x x l x xxxxxxxx x h temporary sector group unprotection * 6 x x x h x xxxxxxxx x v id reset xxxx x xxxxxxxxhigh-z l
mbm29xl12df -70/80 10 mbm29xl12df user bus operations table (dw/w = v ih ) legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see " n dc characteristics" for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see "mbm29xl12df command definitions table". *2 : refer to section on "sector group protection". *3 : we can be v il if oe is v il , oe at v ih initiates the program and erase operations. *4 : v cc = 3.0 v to 3.6 v for 70 ns random access time v cc = 2.7 v to 3.1 v for 80 ns random access time *5 : protects outermost 2 4k words on both end of the boot block sectors. (sa0, sa1, sa268, and sa269) *6 : also used for "extended sector group protection". operation ce oe we wp a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 dq 31 to dq 0 reset autoselect manufacturer code * 1 llh x llllxxlv id code h autoselect device code * 1 llh x hlllxxlv id code h extended autoselect device code * 1 llh x lhhhxxlv id code h l lh x hhhhxx lv id code h read * 3 llh x a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 d out h standby h x x x xxxxxxxxhigh-z h output disable lhh x xxxxxxxxhigh-z h write (program/erase) l h l x a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 9 d in h enable sector group protection * 2, * 4 lv id x lhlhhhlv id xh verify sector group protection * 2, * 4 l lh h lhlhhhlv id code h boot block sector write protection * 5 xxx l xxxxxxxx x h temporary sector group unprotection * 6 xxx h xxxxxxxx x v id reset xxx x xxxxxxxxhigh-z l
mbm29xl12df -70/80 11 mbm29xl12df command definitions table (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 2 xxxh f0hrard read/reset * 1 dw 4 555h aah 2aah 55h 555h f0hrard w aaah 555h aaah autoselect dw 3 555h aah 2aah 55h (ba) 555h 90h w aaah 555h aaah program dw 4 555h aah 2aah 55h 555h a0hpapd w aaah 555h aaah chip erase dw 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h w aaah 555h aaah aaah 555h aaah sector erase dw 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h w aaah 555h aaah aaah 555h program/erase suspend 1 bab0h program/erase resume 1 ba30h set to fast mode dw 3 555h aah 2aah 55h 555h 20h w aaah 555h aaah fast program * 2 dw 2 xxxh a0hpapd w xxxh reset from fast mode * 2 dw 2 ba 90h xxxh f0h * 6 w ba xxxh extended sector group protection* 3 dw 4 xxxh 60hsga60hsga40hsgasd w query * 4 dw 1 (ba) 55h 98h w (ba) 55h hiddenrom entry dw 3 555h aah 2aah 55h 555h 88h w aaah 555h aaah hiddenrom program * 5 dw 4 555h aah 2aah 55h 555h a0h (hra) pa pd w aaah 555h aaah hiddenrom exit * 5 dw 4 555h aah 2aah 55h 555h 90h xxxh 00h w aaah 555h aaah
mbm29xl12df -70/80 12 (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data hiddenrom protect * 5 dw 6 555h aah 2aah 55h 555h 60h opbp 68h opbp 48h xxxh rd (0) w aaah 555h aaah password program * 7 dw 4 555h aah 2aah 55h 555h 38h xx0h pd0 xx1h pd1 w aaah 555h aaah xx0h pd0 xx1h pd1 xx2h pd2 xx3h pd3 password unlock dw 5 555h aah 2aah 55h 555h 28h xx0h pd0 xx1h pd1 w 7 aaah 555h aaah xx2h pd2 xx3h pd3 password verify dw 3 555h aah 2aah 55h 555h c8h pwa pwd w aaah 555h aaah password mode locking bit program dw 6 555h aah 2aah 55h 555h 60h pl 68h pl 48h xxh rd (0) w aaah 555h aaah persistent sector protection mode locking bit program dw 6 555h aah 2aah 55h 555h 60h spml 68h spml 48h xxh rd (0) w aaah 555h aaah ppb program dw 6 555h aah 2aah 55h 555h 60h (sga) wp 68h (sga) wp 48h xx rd (0) w aaah 555h aaah ppb verify dw 4 555h aah 2aah 55h 555h 58h sa rd (0) w aaah 555h aaah all ppb erase * 8 dw 6 555h aah 2aah 55h 555h 60h ep 60h ep 40h xx rd (0) w aaah 555h aaah ppb lock bit set dw 3 555h aah 2aah 55h 555h 78h w aaah 555h aaah ppb lock bit verify dw 4 555h aah 2aah 55h (ba) 555h 58h sa rd (1) w aaah 555h aaah dpb write dw 4 555h aah 2aah 55h 555h 48h sa x1h w aaah 555h aaah dpb erase dw 4 555h aah 2aah 55h 555h 48h sa x0h w aaah 555h aaah dpb/ppb verify dw 4 555h aah 2aah 55h (ba) 555h 58h sa rd (0) w aaah 555h aaah
mbm29xl12df -70/80 13 legend : ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector ba = bank address rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. sga = sector group address to be protected. set sector group address and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0) sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area(double word mode: 000000h to 00003fh) (word mode : 000000h to 00007fh) rd(0) = dq 0 data, rd(1) = dq 1 data. ppb lock bit is read on dq 1 and ppb or dpb are read on dq 0 . if set, dq 0 /dq 1 =1. if cleared, dq 0 /dq 1 =0. opbp = (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 1, 0, 1, 0) 64 bit password data pd0 to pd1 : double word mode pd0 to pd3 : word mode pwa/pwd = password address/password data pl = password locking address (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 0, 1, 0, 1, 0) spml = persistent protection mode locking (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (x, 0, 1, 0, 0, 1, 0) wp = ppb program (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 1, 1, 1, 0, 1, 0) ep = ppb erase (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (1, 1, 1, 1, 0, 1, 0) *1 : both of these reset commands are equivalent. *2 : this command is valid during fast mode. *3 : this command is valid while reset = v id . *4 : the valid addresses are a 6 to a 0 . *5 : this command is valid during hiddenrom mode. *6 : the data 00h is also acceptable. *7 : data before fourth cycle also need to be programmed repearting from first cycle to third cycle. *8 : rd(0) of the sixth cycle shows ppb erase status. when rd(0) is "1", programming must be repeated from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase. notes : address bits a 21 to a 11 = x = h or l for all address commands except for pa, sa, ba, sga, opbp, pwa, pl, spml, wp. bus operations are defined in "mbm29xl12df user bus operations table (dw/w = v il )" and "mbm29xl12df user bus operations table (dw/w = v ih )". the system should generate the following address patterns: dw (double word) mode : 555h or 2aah to addresses a 10 to a 0 w (word) mode : aaah or 555h to addresses a 10 to a 0 , a -1 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in command definitions table are illegal.
mbm29xl12df -70/80 14 mbm29xl12df autoselect codes table *1 : a -1 is for word mode. *2 : sector group can be protected by "sector group protection", "extended sector group protection" and "new sector protection(ppb protection)". outputs 01h at protected ppb addresses and outputs 00h at unprotected ppb addresses. *3 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simutaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. *4 : at double word mode, a read cycle at address (ba) 01h (at word mode,02h) outputs device code. when 222227eh (at word mode,227eh) is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at word mode,1ch), as well as at (ba) 0fh (at word mode, 1eh). type a 21 to a 11 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a -1 * 1 code (hex) manufactures code ba* 3 v il xxv il v il v il v il v il 04h device code double word ba* 3 v il xxv il v il v il v ih x 2222227eh word v il 227eh extended device code* 4 double word ba* 3 v il xxv ih v ih v ih v il x 2222220dh word v il 220dh double word ba* 3 v il xxv ih v ih v ih v ih x 22222200h word v il 2200h ppb protection sector group addresses v il v ih v ih v ih v il v ih v il v il 01h* 2
mbm29xl12df -70/80 15 exteneded auteselect code table hz : high-z (dw) : double word mode (w) : word mode * : in word mode, dq 30 to dq 16 become "high-z" and dq 31 becomes lowest address "a -1 ". type code dq 31 dq 30 dq 29 dq 28 dq 27 dq 26 dq 25 dq 24 dq 23 dq 22 dq 21 dq 20 dq 19 dq 18 dq 17 dq 16 manufacturers code 04h a -1 /0000000000000000 device code (dw) 2222 227eh 0010001000100010 (w) 227eh a -1 hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz extended device code (dw) 2222 220dh 0010001000100010 (w) 220dh a -1 hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz (dw) 2222 2200h 0010001000100010 (w) 2200h a -1 hz hz hz hz hz hz hz hz hz hz hz hz hz hz hz ppb protection 01h a -1 /0000000000000000 ppb unprotection 00h a -1 /0000000000000000 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h 0000000000000100 device code (dw) 2222 227eh 0010001001111110 (w) 227eh 0010001001111110 extended device code (dw) 2222 220dh 0010001000001101 (w) 220dh 0010001000001101 (dw) 2222 2200h 0010001000000000 (w) 2200h 0010001000000000 ppb protection * 01h 0000000000000001 ppb unprotection * 00h 0000000000000000
mbm29xl12df -70/80 16 sector address tables (bank a) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank a sa0 0 0 0 0 0 0 0 0 0 0 0 4/2 000000h to 000fffh 000000h to 0007ffh sa1 0 0 0 0 0 0 0 0 0 0 1 4/2 001000h to 001fffh 000800h to 000fffh sa2 0 0 0 0 0 0 0 0 0 1 0 4/2 002000h to 002fffh 001000h to 0017ffh sa3 0 0 0 0 0 0 0 0 0 1 1 4/2 003000h to 003fffh 001800h to 001fffh sa4 0 0 0 0 0 0 0 0 1 0 0 4/2 004000h to 004fffh 002000h to 0027ffh sa5 0 0 0 0 0 0 0 0 1 0 1 4/2 005000h to 005fffh 002800h to 002fffh sa6 0 0 0 0 0 0 0 0 1 1 0 4/2 006000h to 006fffh 003000h to 0037ffh sa7 0 0 0 0 0 0 0 0 1 1 1 4/2 007000h to 007fffh 003800h to 003fffh sa8 0 0 0 0 0 0 0 1 x x x 32/16 008000h to 00ffffh 004000h to 007fffh sa9 0 0 0 0 0 0 1 0 x x x 32/16 010000h to 017fffh 008000h to 00bfffh sa10 0 0 0 0 0 0 1 1 x x x 32/16 018000h to 01ffffh 00c000h to 00ffffh sa11 0 0 0 0 0 1 0 0 x x x 32/16 020000h to 027fffh 010000h to 013fffh sa12 0 0 0 0 0 1 0 1 x x x 32/16 028000h to 02ffffh 014000h to 017fffh sa13 0 0 0 0 0 1 1 0 x x x 32/16 030000h to 037fffh 018000h to 01bfffh sa14 0 0 0 0 0 1 1 1 x x x 32/16 038000h to 03ffffh 01c000h to 01ffffh sa15 0 0 0 0 1 0 0 0 x x x 32/16 040000h to 047fffh 020000h to 023fffh sa16 0 0 0 0 1 0 0 1 x x x 32/16 048000h to 04ffffh 024000h to 027fffh sa17 0 0 0 0 1 0 1 0 x x x 32/16 050000h to 057fffh 028000h to 02bfffh sa18 0 0 0 0 1 0 1 1 x x x 32/16 058000h to 05ffffh 02c000h to 02ffffh sa19 0 0 0 0 1 1 0 0 x x x 32/16 060000h to 067fffh 030000h to 033fffh sa20 0 0 0 0 1 1 0 1 x x x 32/16 068000h to 06ffffh 034000h to 037fffh sa21 0 0 0 0 1 1 1 0 x x x 32/16 070000h to 077fffh 038000h to 03bfffh sa22 0 0 0 0 1 1 1 1 x x x 32/16 078000h to 07ffffh 03c000h to 03ffffh sa23 0 0 0 1 0 0 0 0 x x x 32/16 080000h to 087fffh 040000h to 043fffh sa24 0 0 0 1 0 0 0 1 x x x 32/16 088000h to 08ffffh 044000h to 047fffh sa25 0 0 0 1 0 0 1 0 x x x 32/16 090000h to 097fffh 048000h to 04bfffh sa26 0 0 0 1 0 0 1 1 x x x 32/16 098000h to 09ffffh 04c000h to 04ffffh sa27 0 0 0 1 0 1 0 0 x x x 32/16 0a0000h to 0a7fffh 050000h to 053fffh sa28 0 0 0 1 0 1 0 1 x x x 32/16 0a8000h to 0affffh 054000h to 057fffh sa29 0 0 0 1 0 1 1 0 x x x 32/16 0b0000h to 0b7fffh 058000h to 05bfffh sa30 0 0 0 1 0 1 1 1 x x x 32/16 0b8000h to 0bffffh 05c000h to 05ffffh sa31 0 0 0 1 1 0 0 0 x x x 32/16 0c0000h to 0c7fffh 060000h to 063fffh sa32 0 0 0 1 1 0 0 1 x x x 32/16 0c8000h to 0cffffh 064000h to 067fffh sa33 0 0 0 1 1 0 1 0 x x x 32/16 0d0000h to 0d7fffh 068000h to 06bfffh sa34 0 0 0 1 1 0 1 1 x x x 32/16 0d8000h to 0dffffh 06c000h to 06ffffh sa35 0 0 0 1 1 1 0 0 x x x 32/16 0e0000h to 0e7fffh 070000h to 073fffh sa36 0 0 0 1 1 1 0 1 x x x 32/16 0e8000h to 0effffh 074000h to 077fffh sa37 0 0 0 1 1 1 1 0 x x x 32/16 0f0000h to 0f7fffh 078000h to 07bfffh sa38 0 0 0 1 1 1 1 1 x x x 32/16 0f8000h to 0fffffh 07c000h to 07ffffh
mbm29xl12df -70/80 17 sector address tables (bank b) (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank b sa39 00100000xxx 32/16 100000h to 107 fffh 080000h to 083fffh sa40 00100001xxx 32/16 108000h to 10 ffffh 084000h to 087fffh sa41 00100010xxx 32/16 110000h to 117 fffh 088000h to 08bfffh sa42 00100011xxx 32/16 118000h to 11 ffffh 08c000h to 08ffffh sa43 00100100xxx 32/16 120000h to 127 fffh 090000h to 093fffh sa44 00100101xxx 32/16 128000h to 12 ffffh 094000h to 097fffh sa45 00100110xxx 32/16 130000h to 137 fffh 098000h to 09bfffh sa46 00100111xxx 32/16 138000h to 13 ffffh 09c000h to 09ffffh sa47 00101000xxx 32/16 140000h to 147 fffh 0a0000h to 0a3fffh sa48 00101001xxx 32/16 148000h to 14 ffffh 0a4000h to 0a7fffh sa49 00101010xxx 32/16 150000h to 157 fffh 0a8000h to 0abfffh sa50 00101011xxx 32/16 158000h to 15 ffffh 0ac000h to 0affffh sa51 00101100xxx 32/16 160000h to 167 fffh 0b0000h to 0b3fffh sa52 00101101xxx 32/16 168000h to 16 ffffh 0b4000h to 0b7fffh sa53 00101110xxx 32/16 170000h to 177 fffh 0b8000h to 0bbfffh sa54 00101111xxx 32/16 178000h to 17 ffffh 0bc000h to 0bffffh sa55 00110000xxx 32/16 180000h to 187 fffh 0c0000h to 0c3fffh sa56 00110001xxx 32/16 188000h to 18 ffffh 0c4000h to 0c7fffh sa57 00110010xxx 32/16 190000h to 197 fffh 0c8000h to 0cbfffh sa58 00110011xxx 32/16 198000h to 19 ffffh 0cc000h to 0cffffh sa59 00110100xxx 32/16 1a0000h to 1a7 fffh 0d0000h to 0d3fffh sa60 00110101xxx 32/16 1a8000h to 1a ffffh 0d4000h to 0d7fffh sa61 00110110xxx 32/16 1b0000h to 1b7 fffh 0d8000h to 0dbfffh sa62 00110111xxx 32/16 1b8000h to 1b ffffh 0dc000h to 0dffffh sa63 00111000xxx 32/16 1c0000h to 1c7 fffh 0e0000h to 0e3fffh sa64 00111001xxx 32/16 1c8000h to 1cffffh0e4000h to 0e7 fffh sa65 00111010xxx 32/16 1d0000h to 1d7 fffh 0e8000h to 0ebfffh sa66 00111011xxx 32/16 1d8000h to 1dffffh0ec000h to 0e ffffh sa67 00111100xxx 32/16 1e0000h to 1e7 fffh 0f0000h to 0f3fffh sa68 00111101xxx 32/16 1e8000h to 1e ffffh 0f4000h to 0f7fffh sa69 00111110xxx 32/16 1f0000h to 1f7 fffh 0f8000h to 0fbfffh sa70 00111111xxx 32/16 1f8000h to 1 fffffh 0fc000h to 0fffffh sa71 01000000xxx 32/16 200000h to 207 fffh 100000h to 103fffh sa72 01000001xxx 32/16 208000h to 20 ffffh 104000h to 107fffh sa73 01000010xxx 32/16 210000h to 217 fffh 108000h to 10bfffh sa74 01000011xxx 32/16 218000h to 21 ffffh 10c000h to 10ffffh sa75 01000100xxx 32/16 220000h to 227 fffh 110000h to 113fffh sa76 01000101xxx 32/16 228000h to 22 ffffh 114000h to 117fffh sa77 01000110xxx 32/16 230000h to 237 fffh 118000h to 11bfffh
mbm29xl12df -70/80 18 (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank b sa78 01000111xxx 32/16 238000h to 23 ffffh 11c000h to 11ffffh sa79 01001000xxx 32/16 240000h to 247 fffh 120000h to 123fffh sa80 01001001xxx 32/16 248000h to 24 ffffh 124000h to 127fffh sa81 01001010xxx 32/16 250000h to 257 fffh 128000h to 12bfffh sa82 01001011xxx 32/16 258000h to 25 ffffh 12c000h to 12ffffh sa83 01001100xxx 32/16 260000h to 267 fffh 130000h to 133fffh sa84 01001101xxx 32/16 268000h to 26 ffffh 134000h to 137fffh sa85 01001110xxx 32/16 270000h to 277 fffh 138000h to 13bfffh sa86 01001111xxx 32/16 278000h to 27 ffffh 13c000h to 13ffffh sa87 01010000xxx 32/16 280000h to 287 fffh 140000h to 143fffh sa88 01010001xxx 32/16 288000h to 28 ffffh 144000h to 147fffh sa89 01010010xxx 32/16 290000h to 297 fffh 148000h to 14bfffh sa90 01010011xxx 32/16 298000h to 29 ffffh 14c000h to 14ffffh sa91 01010100xxx 32/16 2a0000h to 2a7 fffh 150000h to 153fffh sa92 01010101xxx 32/16 2a8000h to 2a ffffh 154000h to 157fffh sa93 01010110xxx 32/16 2b0000h to 2b7 fffh 158000h to 15bfffh sa94 01010111xxx 32/16 2b8000h to 2b ffffh 15c000h to 15ffffh sa95 01011000xxx 32/16 2c0000h to 2c7fffh 160000h to 163 fffh sa96 01011001xxx 32/16 2c8000h to 2c ffffh 164000h to 167fffh sa97 01011010xxx 32/16 2d0000h to 2d7fffh 168000h to 16b fffh sa98 01011011xxx 32/16 2d8000h to 2d ffffh 16c000h to 16ffffh sa99 01011100xxx 32/16 2e0000h to 2e7 fffh 170000h to 173fffh sa10001011101xxx 32/16 2e8000h to 2e ffffh 174000h to 177fffh sa10101011110xxx 32/16 2f0000h to 2f7 fffh 178000h to 17bfffh sa10201011111xxx 32/16 2f8000h to 2 fffffh 17c000h to 17ffffh sa10301100000xxx 32/16 300000h to 307 fffh 180000h to 183fffh sa10401100001xxx 32/16 308000h to 30 ffffh 184000h to 187fffh sa10501100010xxx 32/16 310000h to 317 fffh 188000h to 18bfffh sa10601100011xxx 32/16 318000h to 31 ffffh 18c000h to 18ffffh sa10701100100xxx 32/16 320000h to 327 fffh 190000h to 193fffh sa10801100101xxx 32/16 328000h to 32 ffffh 194000h to 197fffh sa10901100110xxx 32/16 330000h to 337 fffh 198000h to 19bfffh sa11001100111xxx 32/16 338000h to 33 ffffh 19c000h to 19ffffh sa11101101000xxx 32/16 340000h to 347 fffh 1a0000h to 1a3fffh sa11201101001xxx 32/16 348000h to 34 ffffh 1a4000h to 1a7fffh sa11301101010xxx 32/16 350000h to 357 fffh 1a8000h to 1abfffh sa11401101011xxx 32/16 358000h to 35 ffffh 1ac000h to 1affffh sa11501101100xxx 32/16 360000h to 367 fffh 1b0000h to 1b3fffh sa11601101101xxx 32/16 368000h to 36 ffffh 1b4000h to 1b7fffh
mbm29xl12df -70/80 19 (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank b sa11701101110xxx 32/16 370000h to 377fffh 1b8000h to 1bb fffh sa11801101111xxx 32/16 378000h to 37 ffffh 1bc000h to 1bffffh sa11901110000xxx 32/16 380000h to 387fffh 1c0000h to 1c3fffh sa12001110001xxx 32/16 388000h to 38 ffffh 1c4000h to 1c7fffh sa12101110010xxx 32/16 390000h to 397fffh 1c8000h to 1cb fffh sa12201110011xxx 32/16 398000h to 39 ffffh 1cc000h to 1cffffh sa12301110100xxx 32/16 3a0000h to 3a7 fffh 1d0000h to 1d3fffh sa12401110101xxx 32/16 3a8000h to 3a ffffh 1d4000h to 1d7fffh sa12501110110xxx 32/16 3b0000h to 3b7 fffh 1d8000h to 1dbfffh sa12601110111xxx 32/16 3b8000h to 3b ffffh 1dc000h to 1dffffh sa12701111000xxx 32/16 3c0000h to 3c7 fffh 1e0000h to 1e3fffh sa12801111001xxx 32/16 3c8000h to 3c ffffh 1e4000h to 1e7fffh sa12901111010xxx 32/16 3d0000h to 3d7 fffh 1e8000h to 1ebfffh sa13001111011xxx 32/16 3d8000h to 3d ffffh 1ec000h to 1effffh sa13101111100xxx 32/16 3e0000h to 3e7 fffh 1f0000h to 1f3fffh sa13201111101xxx 32/16 3e8000h to 3e ffffh 1f4000h to 1f7fffh sa13301111110xxx 32/16 3f0000h to 3f7 fffh 1f8000h to 1fbfffh sa13401111111xxx 32/16 3f8000h to 3 fffffh 1fc000h to 1fffffh
mbm29xl12df -70/80 20 sector address tables (bank c) (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank c sa13510000000xxx 32/16 400000h to 407 fffh 200000h to 203fffh sa13610000001xxx 32/16 408000h to 40 ffffh 204000h to 207fffh sa13710000010xxx 32/16 410000h to 417 fffh 208000h to 20bfffh sa13810000011xxx 32/16 418000h to 41 ffffh 20c000h to 20ffffh sa13910000100xxx 32/16 420000h to 427 fffh 210000h to 213fffh sa14010000101xxx 32/16 428000h to 42 ffffh 214000h to 217fffh sa14110000110xxx 32/16 430000h to 437 fffh 218000h to 21bfffh sa14210000111xxx 32/16 438000h to 43 ffffh 21c000h to 21ffffh sa14310001000xxx 32/16 440000h to 447 fffh 220000h to 223fffh sa14410001001xxx 32/16 448000h to 44 ffffh 224000h to 227fffh sa14510001010xxx 32/16 450000h to 457 fffh 228000h to 22bfffh sa14610001011xxx 32/16 458000h to 45 ffffh 22c000h to 22ffffh sa14710001100xxx 32/16 460000h to 467 fffh 230000h to 233fffh sa14810001101xxx 32/16 468000h to 46 ffffh 234000h to 237fffh sa14910001110xxx 32/16 470000h to 477 fffh 238000h to 23bfffh sa15010001111xxx 32/16 478000h to 47 ffffh 23c000h to 23ffffh sa15110010000xxx 32/16 480000h to 487 fffh 240000h to 243fffh sa15210010001xxx 32/16 488000h to 48 ffffh 244000h to 247fffh sa15310010010xxx 32/16 490000h to 497 fffh 248000h to 24bfffh sa15410010011xxx 32/16 498000h to 49 ffffh 24c000h to 24ffffh sa15510010100xxx 32/16 4a0000h to 4a7 fffh 250000h to 253fffh sa15610010101xxx 32/16 4a8000h to 4af fffh 254000h to 257fffh sa15710010110xxx 32/16 4b0000h to 4b7 fffh 258000h to 25bfffh sa15810010111xxx 32/16 4b8000h to 4bf fffh 25c000h to 25ffffh sa15910011000xxx 32/16 4c0000h to 4c7 fffh 260000h to 263fffh sa16010011001xxx 32/16 4c8000h to 4c ffffh 264000h to 267fffh sa16110011010xxx 32/16 4d0000h to 4d7 fffh 268000h to 26bfffh sa16210011011xxx 32/16 4d8000h to 4d ffffh 26c000h to 26ffffh sa16310011100xxx 32/16 4e0000h to 4e7 fffh 270000h to 273fffh sa16410011101xxx 32/16 4e8000h to 4ef fffh 274000h to 277fffh sa16510011110xxx 32/16 4f0000h to 4f7 fffh 278000h to 27bfffh sa16610011111xxx 32/16 4f8000h to 4 fffffh 27c000h to 27ffffh sa16710100000xxx 32/16 500000h to 507 fffh 280000h to 283fffh sa16810100001xxx 32/16 508000h to 50 ffffh 284000h to 287fffh sa16910100010xxx 32/16 510000h to 517 fffh 288000h to 28bfffh sa17010100011xxx 32/16 518000h to 51 ffffh 28c000h to 28ffffh sa17110100100xxx 32/16 520000h to 527 fffh 290000h to 293fffh sa17210100101xxx 32/16 528000h to 52 ffffh 294000h to 297fffh sa17310100110xxx 32/16 530000h to 537 fffh 298000h to 29bfffh
mbm29xl12df -70/80 21 (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank c sa17410100111xxx 32/16 538000h to 53 ffffh 29c000h to 29ffffh sa17510101000xxx 32/16 540000h to 547 fffh 2a0000h to 2a3fffh sa17610101001xxx 32/16 548000h to 54 ffffh 2a4000h to 2a7fffh sa17710101010xxx 32/16 550000h to 557 fffh 2a8000h to 2abfffh sa17810101011xxx 32/16 558000h to 55 ffffh 2ac000h to 2affffh sa17910101100xxx 32/16 560000h to 567 fffh 2b0000h to 2b3fffh sa18010101101xxx 32/16 568000h to 56 ffffh 2b4000h to 2b7fffh sa18110101110xxx 32/16 570000h to 577 fffh 2b8000h to 2bbfffh sa18210101111xxx 32/16 578000h to 57 ffffh 2bc000h to 2bffffh sa18310110000xxx 32/16 580000h to 587 fffh 2c0000h to 2c3fffh sa18410110001xxx 32/16 588000h to 58 ffffh 2c4000h to 2c7fffh sa18510110010xxx 32/16 590000h to 597 fffh 2c8000h to 2cbfffh sa18610110011xxx 32/16 598000h to 59 ffffh 2cc000h to 2cffffh sa18710110100xxx 32/16 5a0000h to 5a7 fffh 2d0000h to 2d3fffh sa18810110101xxx 32/16 5a8000h to 5affffh2d4000h to 2d7fffh sa18910110110xxx 32/16 5b0000h to 5b7 fffh 2d8000h to 2dbfffh sa19010110111xxx 32/16 5b8000h to 5bffffh2dc000h to 2df fffh sa19110111000xxx 32/16 5c0000h to 5c7 fffh 2e0000h to 2e3fffh sa19210111001xxx 32/16 5c8000h to 5c ffffh 2e4000h to 2e7fffh sa19310111010xxx 32/16 6d0000h to 5d7 fffh 2e8000h to 2ebfffh sa19410111011xxx 32/16 6d8000h to 5d ffffh 2ec000h to 2effffh sa19510111100xxx 32/16 5e0000h to 5e7 fffh 2f0000h to 2f3fffh sa19610111101xxx 32/16 5e8000h to 5effffh 2f4000h to 2f7 fffh sa19710111110xxx 32/16 5f0000h to 5f7fffh 2f8000h to 2fb fffh sa19810111111xxx 32/16 5f8000h to 5 fffffh 2fc000h to 2fffffh sa19911000000xxx 32/16 600000h to 607 fffh 300000h to 303fffh sa20011000001xxx 32/16 608000h to 60 ffffh 304000h to 307fffh sa20111000010xxx 32/16 610000h to 617 fffh 308000h to 30bfffh sa20211000011xxx 32/16 618000h to 61 ffffh 30c000h to 30ffffh sa20311000100xxx 32/16 620000h to 627 fffh 310000h to 313fffh sa20411000101xxx 32/16 628000h to 62 ffffh 314000h to 317fffh sa20511000110xxx 32/16 630000h to 637 fffh 318000h to 31bfffh sa20611000111xxx 32/16 638000h to 63 ffffh 31c000h to 31ffffh sa20711001000xxx 32/16 640000h to 647 fffh 320000h to 323fffh sa20811001001xxx 32/16 648000h to 64 ffffh 324000h to 327fffh sa20911001010xxx 32/16 650000h to 657 fffh 328000h to 32bfffh sa21011001011xxx 32/16 658000h to 65 ffffh 32c000h to 32ffffh sa21111001100xxx 32/16 660000h to 667 fffh 330000h to 333fffh sa21211001101xxx 32/16 668000h to 66 ffffh 334000h to 337fffh
mbm29xl12df -70/80 22 (continued) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank c sa21311001110xxx 32/16 670000h to 677 fffh 338000h to 33bfffh sa21411001111xxx 32/16 678000h to 67 ffffh 33c000h to 33ffffh sa21511010000xxx 32/16 680000h to 687 fffh 340000h to 343fffh sa21611010001xxx 32/16 688000h to 68 ffffh 344000h to 347fffh sa21711010010xxx 32/16 690000h to 697 fffh 348000h to 34bfffh sa21811010011xxx 32/16 698000h to 69 ffffh 34c000h to 34ffffh sa21911010100xxx 32/16 6a0000h to 6a7 fffh 350000h to 353fffh sa22011010101xxx 32/16 6a8000h to 6a ffffh 354000h to 357fffh sa22111010110xxx 32/16 6b0000h to 6b7 fffh 358000h to 35bfffh sa22211010111xxx 32/16 8b8000h to 6b ffffh 35c000h to 35ffffh sa22311011000xxx 32/16 6c0000h to 6c7 fffh 360000h to 363fffh sa22411011001xxx 32/16 6c8000h to 6c ffffh 364000h to 367fffh sa22511011010xxx 32/16 6d0000h to 6d7 fffh 368000h to 36bfffh sa22611011011xxx 32/16 6d8000h to 6d ffffh 36c000h to 36ffffh sa22711011100xxx 32/16 6e0000h to 6e7 fffh 370000h to 373fffh sa22811011101xxx 32/16 6e8000h to 6e ffffh 374000h to 377fffh sa22911011110xxx 32/16 6f0000h to 6f7 fffh 378000h to 37bfffh sa23011011111xxx 32/16 6f8000h to 6ff fffh 37c000h to 37ffffh
mbm29xl12df -70/80 23 sector address tables (bank d) bank sector sector address sector size (kw / kdw) ( 16) address range ( 32) address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank d sa23111100000xxx 32/16 700000h to 707 fffh 380000h to 383fffh sa23211100001xxx 32/16 708000h to 70 ffffh 384000h to 387fffh sa23311100010xxx 32/16 710000h to 717 fffh 388000h to 38bfffh sa23411100011xxx 32/16 718000h to 71 ffffh 38c000h to 38ffffh sa23511100100xxx 32/16 720000h to 727 fffh 390000h to 393fffh sa23611100101xxx 32/16 728000h to 72 ffffh 394000h to 397fffh sa23711100110xxx 32/16 730000h to 737 fffh 398000h to 39bfffh sa23811100111xxx 32/16 738000h to 73 ffffh 39c000h to 39ffffh sa23911101000xxx 32/16 740000h to 747 fffh 3a0000h to 3a3fffh sa24011101001xxx 32/16 748000h to 74 ffffh 3a4000h to 3a7fffh sa24111101010xxx 32/16 750000h to 757 fffh 3a8000h to 3abfffh sa24211101011xxx 32/16 758000h to 75 ffffh 3ac000h to 3affffh sa24311101100xxx 32/16 760000h to 767 fffh 3b0000h to 3b3fffh sa24411101101xxx 32/16 768000h to 76 ffffh 3b4000h to 3b7fffh sa24511101110xxx 32/16 770000h to 777 fffh 3b8000h to 3bbfffh sa24611101111xxx 32/16 778000h to 77 ffffh 3bc000h to 3bffffh sa24711110000xxx 32/16 780000h to 787 fffh 3c0000h to 3c3fffh sa24811110001xxx 32/16 788000h to 78 ffffh 3c4000h to 3c7fffh sa24911110010xxx 32/16 790000h to 797 fffh 3c8000h to 3cbfffh sa25011110011xxx 32/16 798000h to 79 ffffh 3cc000h to 3cffffh sa25111110100xxx 32/16 7a0000h to 7a7 fffh 3d0000h to 3d3fffh sa25211110101xxx 32/16 7a8000h to 7a ffffh 3d4000h to 3d7fffh sa25311110110xxx 32/16 7b0000h to 7b7 fffh 3d8000h to 3dbfffh sa25411110111xxx 32/16 7b8000h to 7b ffffh 3dc000h to 3dffffh sa25511111000xxx 32/16 7c0000h to 7c7 fffh 3e0000h to 3e3fffh sa25611111001xxx 32/16 7c8000h to 7c ffffh 3e4000h to 3e7fffh sa25711111010xxx 32/16 7d0000h to 7d7 fffh 3e8000h to 3ebfffh sa25811111011xxx 32/16 7d8000h to 7d ffffh 3ec000h to 3effffh sa25911111100xxx 32/16 7e0000h to 7e7 fffh 3f0000h to 3f3fffh sa26011111101xxx 32/16 7e8000h to 7e ffffh 3f4000h to 3f7fffh sa26111111110xxx 32/16 7f0000h to 7f7 fffh 3f8000h to 3fbfffh sa26211111111000 4/2 7f8000h to 7f8 fffh 3fc000h to 3fc7ffh sa26311111111001 4/2 7f9000h to 7f9 fffh 3fc800h to 3fcfffh sa26411111111010 4/2 7fa000h to 7fa fffh 3fd000h to 3fd7ffh sa26511111111011 4/2 7fb000h to 7fb fffh 3fd800h to 3fdfffh sa26611111111100 4/2 7fc000h to 7fc fffh 3fe000h to 3fe7ffh sa26711111111101 4/2 7fd000h to 7fd fffh 3fe800h to 3fefffh sa26811111111110 4/2 7fe000h to 7fe fffh 3ff000h to 3ff7ffh sa26911111111111 4/2 7ff000h to 7 fffffh 3ff800h to 3fffffh
mbm29xl12df -70/80 24 sector group address table (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 sectors sga0 00000000000 sa0 sga1 00000000001 sa1 sga2 00000000010 sa2 sga3 00000000011 sa3 sga4 00000000100 sa4 sga5 00000000101 sa5 sga6 00000000110 sa6 sga7 00000000111 sa7 sga8 000000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 0 0 1 x x x x x sa11 to sa14 sga10 0 0 0 0 1 0 x x x x x sa15 to sa18 sga11 0 0 0 0 1 1 x x x x x sa19 to sa22 sga12 0 0 0 1 0 0 x x x x x sa23 to sa26 sga13 0 0 0 1 0 1 x x x x x sa27 to sa30 sga14 0 0 0 1 1 0 x x x x x sa31 to sa34 sga15 0 0 0 1 1 1 x x x x x sa35 to sa38 sga16 0 0 1 0 0 0 x x x x x sa39 to sa42 sga17 0 0 1 0 0 1 x x x x x sa43 to sa46 sga18 0 0 1 0 1 0 x x x x x sa47 to sa50 sga19 0 0 1 0 1 1 x x x x x sa51 to sa54 sga20 0 0 1 1 0 0 x x x x x sa55 to sa58 sga21 0 0 1 1 0 1 x x x x x sa59 to sa62 sga22 0 0 1 1 1 0 x x x x x sa63 to sa66 sga23 0 0 1 1 1 1 x x x x x sa67 to sa70 sga24 0 1 0 0 0 0 x x x x x sa71 to sa74 sga25 0 1 0 0 0 1 x x x x x sa75 to sa78 sga26 0 1 0 0 1 0 x x x x x sa79 to sa82 sga27 0 1 0 0 1 1 x x x x x sa83 to sa86 sga28 0 1 0 1 0 0 x x x x x sa87 to sa90 sga29 0 1 0 1 0 1 x x x x x sa91 to sa94 sga30 0 1 0 1 1 0 x x x x x sa95 to sa98 sga31 0 1 0 1 1 1 x x x x x sa99 to sa102 sga32 0 1 1 0 0 0 x x x x x sa103 to sa106
mbm29xl12df -70/80 25 (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 sectors sga33 0 1 1 0 0 1 x x x x x sa107 to sa110 sga34 0 1 1 0 1 0 x x x x x sa111 to sa114 sga35 0 1 1 0 1 1 x x x x x sa115 to sa118 sga36 0 1 1 1 0 0 x x x x x sa119 to sa122 sga37 0 1 1 1 0 1 x x x x x sa123 to sa126 sga38 0 1 1 1 1 0 x x x x x sa127 to sa130 sga39 0 1 1 1 1 1 x x x x x sa131 to sa134 sga40 1 0 0 0 0 0 x x x x x sa135 to sa138 sga41 1 0 0 0 0 1 x x x x x sa139 to sa142 sga42 1 0 0 0 1 0 x x x x x sa143 to sa146 sga43 1 0 0 0 1 1 x x x x x sa147 to sa150 sga44 1 0 0 1 0 0 x x x x x sa151 to sa154 sga45 1 0 0 1 0 1 x x x x x sa155 to sa158 sga46 1 0 0 1 1 0 x x x x x sa159 to sa162 sga47 1 0 0 1 1 1 x x x x x sa163 to sa166 sga48 1 0 1 0 0 0 x x x x x sa167 to sa170 sga49 1 0 1 0 0 1 x x x x x sa171 to sa174 sga50 1 0 1 0 1 0 x x x x x sa175 to sa178 sga51 1 0 1 0 1 1 x x x x x sa179 to sa182 sga52 1 0 1 1 0 0 x x x x x sa183 to sa186 sga53 1 0 1 1 0 1 x x x x x sa187 to sa190 sga54 1 0 1 1 1 0 x x x x x sa191 to sa194 sga55 1 0 1 1 1 1 x x x x x sa195 to sa198 sga56 1 1 0 0 0 0 x x x x x sa199 to sa202 sga57 1 1 0 0 0 1 x x x x x sa203 to sa206 sga58 1 1 0 0 1 0 x x x x x sa207 to sa210 sga59 1 1 0 0 1 1 x x x x x sa211 to sa214 sga60 1 1 0 1 0 0 x x x x x sa215 to sa218 sga61 1 1 0 1 0 1 x x x x x sa219 to sa222 sga62 1 1 0 1 1 0 x x x x x sa223 to sa226 sga63 1 1 0 1 1 1 x x x x x sa227 to sa230 sga64 1 1 1 0 0 0 x x x x x sa231 to sa234 sga65 1 1 1 0 0 1 x x x x x sa235 to sa238 sga66 1 1 1 0 1 0 x x x x x sa239 to sa242 sga67 1 1 1 0 1 1 x x x x x sa243 to sa246
mbm29xl12df -70/80 26 (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 sectors sga68 1 1 1 1 0 0 x x x x x sa247 to sa250 sga69 1 1 1 1 0 1 x x x x x sa251 to sa254 sga70 1 1 1 1 1 0 x x x x x sa255 to sa258 sga71 1 1 1 1 1 1 00 x x x sa259 to sa261 01 10 sga72 11111111000 sa262 sga73 11111111001 sa263 sga74 11111111010 sa264 sga75 11111111011 sa265 sga76 11111111100 sa266 sga77 11111111101 sa267 sga78 11111111110 sa268 sga79 11111111111 sa269
mbm29xl12df -70/80 27 common flash memory interface code (continued) description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 02h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min (write/erase)dq 7 to dq 4 =1v, dq 3 to dq 0 =100 mv 1bh 0027h v cc max (write/erase)dq 7 to dq 4 =1v, dq 3 to dq 0 =100 mv 1ch 0036h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min size buffer write 2 n m s 20h 0000h typical timeout per individual sector erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical m s 23h 0005h max timeout for buffer write 2 n times typical m s 24h 0000h max timeout per individual sector erase 2 n times typical ms 25h 0004h max timeout for full chip erase 2 n times typical ms 26h 0000h device size = 2 n byte 27h 0018h flash device interface description 05h: 16 / 32 28h 29h 0005h 0000h max number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0003h erase block region 1 information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z 256 bytes) 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z 256 bytes) 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 3 information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z 256 bytes) 35h 36h 37h 38h 0007h 0000h 0020h 0000h
mbm29xl12df -70/80 28 (continued) description a 6 to a 0 dq 15 to dq 0 erase block region 4 information bit 15 to 0: y = number of sectors bit 31 to 16: z = size (z 256 bytes) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0033h address sensitive unlock 04h = required and 0.17 m m technology 45h 0004h erase suspend 02h = to read & write 46h 0002h sector protection 00h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotection 01h = supported 48h 0001h sector protection algorithm 49h 0007h dual operation 00h = not supported, x = total number of sectors in all banks except bank a 4ah 00e7h burst mode type 00h = not supported 4bh 0000h page mode type 02h = 8 word page 4ch 0002h v acc (acceleration) supply minimum dq 7 to dq 4 =1v, dq 3 to dq 0 =100 mv 4dh 00b5h v acc (acceleration) supply maximum dq 7 to dq 4 =1v, dq 3 to dq 0 =100 mv 4eh 00c5h boot type 4fh 0001h program suspend, 01h = supported 50h 0001h bank organization x = number of banks 57h 0004h bank a region information x = number of sectors in bank a 58h 0027h bank b region information x = number of sectors in bank b 59h 0060h bank c region information x = number of sectors in bank c 5ah 0060h bank d region information x = number of sectors in bank d 5bh 0027h
mbm29xl12df -70/80 29 n functional description simultaneous operation the device features functions that enable data reading from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . the bank is selected by bank address ( a 21 , a 20 , a 19 ) with zero latency. the device consists of the following four banks : bank a : 8 4kw and 31 32kw; bank b : 96 32 kw; bank c : 96 32kw; bank d : 8 4kw and 31 32kw. the device can execute simultaneous operations between bank 1, a bank chosen from among the four banks, and bank 2, a bank consisting of the three remaining banks. see flexbank tm architecture below. this is what we call flexbank, for example the rest of banks b, c and d to let the system read while bank a is in the process of program (or erase) operation. however the different types of operations for the three banks are not allowed, e.g. bank a programming, bank b erasing, and bank c reading out. with this flexbank, as described in example of virtual banks combination, the system gets to select from four combinations of data volume for bank 1 and bank 2, which works well to meet the system requirement. the simultaneous operation cannot execute multi-function mode in the same bank. refer to bank-to-bank read/write(program and erase) timing diagram. flexbank tm architecture example of virtual banks combination note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, suppose that erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out they output the sequence flag once they are selected. meanwhile the system would get to read from either bank c or bank d. bank splits bank 1 bank 2 bank size combination bank size combination 1 16 mbit bank a 112 mbit bank b, c, d 2 48 mbit bank b 80 mbit bank a, c, d 3 48 mbit bank c 80 mbit bank a, b, d 4 16 mbit bank d 112 mbit bank a, b, c bank splits bank 1 bank 2 bank size combination of memory bank sector sizes bank size combination of memory bank sector sizes 1 16 mbit bank a 8 4k words, 31 32k words 112 mbit bank b + bank c + bank d 8 4k words, 223 32k words 232 mbit bank a + bank d 16 4k words, 62 32k words 96 mbit bank b + bank c 192 32k words 3 48 mbit bank b 96 32k words 80 mbit bank a + bank c + bank d 16 4k words, 158 32k words 464 mbit bank a + bank b 8 4k words, 127 32kwords 64 mbit bank c + bank d 8 4k words, 127 32kwords
mbm29xl12df -70/80 30 simultaneous operation note : bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. the bank consists of 4 banks, bank a, bank b, bankc and bank d. bank address (ba) means to specify each of the banks. read mode the device has two control functions required to obtain data at the outputs. ce is the power control and used for a device selection. oe is the output control and used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. assuming the addresses have been stable for at least t acc - t oe time. when reading out a data without changing addresses after power-up, input hardware reset or to change ce pin from h or l. page mode read the device is capable of fast page mode read and are compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words or 4 double words, within the appropriate page being selected by the higher address bits a 21 to a 2 and the lsb bits a 1 to a 0 (in the double word mode) and a 1 to a -1 (in the word mode) determining the specific double word or word within that page. this is an asynchronous operation with the microprocessor supplying the specific double word or word location. the random or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pa c c . here again, ce selects the device and oe is the output control and used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 21 to a 2 constant and changing a 1 to a 0 to select the specific double word or changing a 1 to a -1 to select the specific word, within that page. standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, cmos standby mode is achieved with ce and reset input held at v cc 0.3 v. under this condition the current consumed is less than 5 a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even when ce =h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, cmos standby mode is achieved with reset input held at v ss 0.3 v (ce =h or l) . under this condition the current consumed is less than 5 a max. once the reset pin is set high, the device requires t rh as a wake-up time for output to be valid for read access. during standby mode, the output is in the high impedance state regardless of oe input. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode 5 autoselect mode read mode 6 program mode read mode 7 erase mode read mode
mbm29xl12df -70/80 31 automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of the device data. this is useful in the application such as a handy terminal which requires low power consumption. to activate this mode, the device automatically switches itself to low power mode when addresses remain stable during access time of 150 ns. it is not necessary to control ce , we , and oe on this mode. the current consumed is typically 1 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are continuously read out. when the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. output disable with the oe input is at logic high level (v ih ), output from the device is disabled. this causes the output pins to be in a high impedance state. autoselect autoselect mode allows reading out of a binary code and identifies its manufacturer and type.it is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id on address pin a 9 . three identifier bytes may then be sequenced from the device outputs by toggling addresses. all addresses are dont cares except a 6 to a 0 . the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in command definitions table of n device bus operations. in the command autoselect mode, the bank addresses ba (a 21 , a 20 , a 19 ) must point to a specific bank during the third write bus cycle of the autoselect command. then the autoselect data are read from that bank while array data can be read from the other bank. a read cycle from address 00h returns the manufacturers code (fujitsu=04h) . a read cycle from address 01h (at word mode, 02h) outputs device code. when 2222227eh (at word mode, 227eh) is output, it indicates that two additional codes, called extended device codes is required. therefore the system may continue reading out these extended device codes at addresses of 0eh (at word mode, 1ch) and 0fh (at word mode, 1eh). refer to autoselect codes table and extended autoselect code table in n device bus operation. in the case of applying v id on a 9 , because both bank 1 and bank 2 enter autoselect mode, simultanous operation cannot be executed. write device erase and programming are accomplished via the command register. the contents of the register serve as input to the internal state machine. the state machine output dictates the device function. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever starts later, while data is latched on the rising edge of we or ce , whichever starts first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters.
mbm29xl12df -70/80 32 double word/word configuration dw/w pin selects double word (32-bit) mode or word (16-bit) mode for the device. when this pin is driven high, device operates in the double word (32-bit) mode. data is read and programmed at dq 31 to dq 0 . when this pin is driven low, device operates in word (16-bit) mode. under this mode, dq 31 /a -1 pin becomes the lowest address bit, and dq 30 to dq 16 bits are tri-stated. however, the command bus cycle is always an 16-bit operation and hence commands are written at dq 15 to dq 0 and dq 31 to dq 16 bits are ignored. refer to double word mode configuration timing diagram,word mode configuration timing diagram and dw/w diagram for write op- erations in n timing diagram. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group becomes temporarily unprotected. the system uses fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore the present sequence is used for programming and detection of completion during acceleration mode. removing v acc from the acc pin and applying v il or v ih returns the device to normal operation. do not remove v acc from acc pin while programming. see accelerated program timing diagram. reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed is terminated and the internal state machine is reset to the read mode t ready after the reset pin is driven low. furthermore once the reset pin goes high the device requires an additional t rh before it allows read access. when the reset pin is low, the device is in the standby mode for the duration of the pulse and all the data output pins are tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location are corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram. hiddenrom region unlike previous flash memory devices, the mbm29xl12df allows simultaneous operation while the hiddenrom is enabled. however, there are a number of restrictions associated with simultaneous operation and device operation when the hiddenrom is enabled: (1) the hiddenrom is not available for reading while the password unlock, any ppb program/erase operation, or password programming are in progress. reading to any location in the bank a will return the status of these operations until these operations have completed execution. (2) writing the corresponding sector protect latch associated with the overlaid bootblock sector results in the sector protect latch not being updated. this is only accomplished when the hiddenrom is not enabled. (3) reading the corresponding dpb associated with the overlaid bootblock sector results in reading invalid data when the ppb lock/dpb verify command is issued. this function is only accomplished when the hiddenrom is not enabled. (4) all commands are available for execution when the hiddenrom is enabled except the following list. issuing the following commands while the hiddenrom is enabled results in the command being ignored. cfi set to fast mode fast program reset from fast mode program and sector erase suspend program and sector erase resume
mbm29xl12df -70/80 33 (5) executing the sector erase command is permitted when the hiddenrom is enabled, however, there is no provision for erasing the hiddenrom with the sector erase command, regardless of the protection status. the sector erase command will erase all other sectors when the hiddenrom is enabled. erasing the hiddenrom with the embedded algorithm is accomplished by issuing the chip erase command. if the hiddenrom is the only sector requiring erasure, set the sector protect latches for the remaining sectors prior to issuing the chip erase command. (6) executing the hiddenrom entry command during program or erase suspend mode is allowed. since the sector erase/program resume command is disabled while the hiddenrom is enabled, the user cannot resume programming or erase of the hiddenrom in place of the overlaid boot block sector. hiddenrom protection bit the hiddenrom protection bit prevents programming of the hiddenrom memory area. once set, the hidden- rom memory area contents are non-modifiable.
mbm29xl12df -70/80 34 the mbm29xl12df features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: (1) write protect (wp )[hardware protection] the device features a hardware protection option using a write protect pin that prevents programming or erasing, regardless of the state of the sectors persistent or dynamic protection bits. the wp pin is associated with the outermost 2 4k words on both ends of boot sectors. the wp pin has no effect on any other sector. when wp is taken to v il , program and erase operations of the outermost 2 4k words sectors on both end are disabled. by taking wp back to v ih , the outermost 2 4k words sectors are enabled for program and erase operations, depending upon the status of the individual sector persistent or dynamic protection bits. if either of the two outermost sectors persistent or dynamic protection bits are programmed, program or erase operations are inhibited. if the sector persistent or dynamic protection bits are both erased, the two sectors are available for programming or erasing as long as wp remains at v ih . the user must hold the wp pin at either v ih or v il during the entire program or erase operation of the outermost two sectors on both end of boot sectors. (2)sector group protection [software protection] the device features hardware sector group protection. this feature disables both program and erase operations in any number of sector groups. the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 ,a 0 ) = (0, 1, 1, 1, 0, 1, 0). the sector addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 , and a 11 ) should be set to the sector group to be protected. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see sector group protection waveforms and algorithms. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 , and a 11 ) while (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 ,a 0 ) = (0, 1, 1, 1, 0, 1, 0) produces logic 1 at device output dq 0 for a protected sector. otherwise the device produces logic "0" for an unprotected sector group. a -1 = v il is required in word mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 , and a 11 ) represents the sector group address will produce a logical 1 at dq 0 for a protected sector. see "user bus operations" for autoselect codes. (3) extended sector group protection [software protection] in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables protection of the sector group by forcing v id on reset pin and writes a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) in the command register. then the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 , and a 11 ) and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0) should be set to the sector group to be protected (setting v il for the other addresses pins is recommended) , and an extended sector group protection command (60h) should be written. a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 , and a 11 ) and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0) should be set a command (40h) should be written. following the command write, logic 1 at device output dq 0 produces a protected sector in the read operation. if the output is logic 0, write the extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . refer to. extended sector group protection waveforms and algorithm.
mbm29xl12df -70/80 35 (4) new sector protection [software protection] a command sector protection method that replaces the old v id controlled protection method in future. however mbm29xl12df supports both v id protection and persistent sector protection. both protect supported as a shift period. the persistent sector protection and the old v id controlled protection can go back each other until persistent protection lock bit is settled. a) persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). all 4 k words boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command. note: if a ppb requires erasure, all of the sector ppbs must first be preprogrammed prior to ppb erasing. all ppbs erase in parallel, unlike programming where individual ppbs are programmable. it is the responsibility of the user to perform the preprogramming operation. otherwise, an already erased sector ppbs has the potential of being over-erased. there is no hardware mechanism to prevent sector ppbs over-erasure. b) dynamic protection bit (dpb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dpbs is 0. each dpb is individually modifiable through the dpb write command. when the parts are first shipped, the ppbs are cleared, the dpbs are cleared, and ppb lock is defaulted to power up in the cleared state - meaning the ppbs are changeable. when the device is first powered on the dpbs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dpb related to that sector. for the sectors that have the ppbs cleared, the dpbs control whether or not the sector is protected or unprotected. by issuing the dpb write/erase command sequences, the dpbs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dpbs maybe set or cleared as often as needed. ppb vs dpb the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the pbb lock bit adds an additional level of protection. once all ppbs are programmed to the desired settings, the ppb lock may be set to 1. setting the ppb lock disables all program and erase commands to the non- volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the pbb lock to disable any further changes to the pbbs during system operation. the wp write protect pin adds a final level of hardware protection to the two outermost 4k words on both ends of boot sectors. when this pin is low it is not possible to change the contents of these two sectors. these sectors generally hold system boot code. so, the wp pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dpb write command sequence is all that is necessary. the dpb write/erase command for the dynamic sectors switch the dpbs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either
mbm29xl12df -70/80 36 putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. note: to achieve the best protection, its recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp = v il . the above table contains all possible combinations of the dpb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the pbb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dpb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 m s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 m s after which the device returns to read mode without having erased the protected sector. the programming of the dpb, ppb, and ppb lock for a given sector can be verified by writing a dpb/ppb/ppb lock verify command to the device. Cdpb/ppb status the programming of the dpb/ppb for a given sector can be verified by writing a dpb/ppb status verify command to the device. Cppb lock bit status the programming of the ppb lock bit for a given sector can be verified by writing a ppb lock bit status verify command to the device. c) persistent protection bit lock (ppb lock) ? ppb locked ? ppb locked with password a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. all parts default to operate in the persistent sector protection mode. the customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit. this will permanently set the part to operate only using persistent sector protection. if the customer decides to use the password protection method, they must set the password mode locking bit. this will permanently set the part to operate only using password sector protection. dpb ppb ppb lock sector state 0 0 0 unprotected ppb and dpb are changeable 1 0 0 protected ppb and dpb and dpb are changeable 0 1 0 protected ppb and dpb and dpb are changeable 1 1 0 protected ppb and dpb and dpb are changeable 001 unprotected ppb not changeable, dpb is changeable 1 0 1 protected ppb not changeable, dpb is changeable 0 1 1 protected ppb not changeable, dpb is changeable 1 1 1 protected ppb not changeable, dpb is changeable
mbm29xl12df -70/80 37 it is important to remember that setting either the persistent sector protection mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the wp hardware protection feature is always available, independent of the software managed protection method chosen. a global volatile bit. when set to 1, the ppbs cannot be changed. when cleared (0), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode locking bit is set, which indicates the device is in password protection mode, the ppb lock bit is also set after a hardware reset (reset asserted) or a power-up reset. the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset , taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit back to a 1. if the password mode locking bit is not set, indicating persistent sector protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent sector protection mode. -password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. fujitsu recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: (1) it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. (2) it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see password verify command). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device.
mbm29xl12df -70/80 38 -persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. (5) temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the device in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. while ppb lock is set, this device cannot enter the temporary sector group unprotection mode.
mbm29xl12df -70/80 39 n command definitions device operations are selected by writing specific address and data sequences into the command register. some commands require bank address (ba) input. when command sequences are input into bank reading, the commands have priority over the reading. "mbm29xl12df command definitions table" in n device bus operation shows the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover, read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 15 to dq 0 and dq 31 to dq 16 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, verify mode of secter protect commands, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device automatically powers-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therefore manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a higher voltage. however multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated first by writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. the higher order address (a 21 , a 20 , a 19 ) required for reading out the manufacture and device codes demands the bank address (ba) set at the third write cycle. following the command write, a read cycle from address (ba) 00h returns the manufacturers code (fujitsu=04h). and, at double word mode, a read cycle at address (ba) 01h (at word mode, 02h) outputs device code. when 2222227eh (at word mode, 227eh) is output, this indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at word mode, 1ch), as well as at (ba) 0fh (at word mode, 1eh). refer to "mbm29xl12df autoselect codes table" and "exteneded auteselect code table" in n device bus operation. the sector state (ppb protection or ppb unprotection) is informed by address (sa) xx02h . scanning the sector group addresses (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 and a 11 ) while(a 6 , a 5 , a 4 , a 3 , a 2 , a 1 ,a 0 ) = (0, 1, 1, 1, 0, 1, 0) produces logic 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verifying sector group protection on the protected sector. see "mbm29xl12df user bus operations table (dw/w = v il )" and "mbm29xl12df user bus operations table (dw/w = v ih )" in n device bus operation. the manufacture and device codes can be read from the selected bank. to read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the read/reset command sequence into the register. autoselect command should then be written into the bank to be read. if the software (program code) for autoselect command is stored in the flash memory, the device and manu- facture codes should be read from the other bank, which does not contain the software.
mbm29xl12df -70/80 40 to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, read/reset command sequence must be written before the autoselect command. word/double word programming command the device is programmed on word-by-word basis (or double word-by-double word). programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later, and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) starts programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device automatically provides adequate inter- nally generated program pulses and verify programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit) or ry/by . the data polling and toggle bit must be performed at the memory location being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which device returns to the read mode and addresses are no longer latched. see "hardware sequence flags". therefore the device requires that a valid address to the device be supplied by the system in this particular instance. hence data polling must be performed at the memory location being programmed. any commands written to the chip during this period are ignored. if hardware reset occurs during the programming operation, the data being written is not guaranteed. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert from 0s to 1s. refer to "embedded program tm algorithm" using typical command strings and bus operations. program suspend/resume command the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended. the bank addresses of sector being programmed should be set when writing the program suspend command. when the program suspend command is written during a programming process, the device halts the program operation within 1 m s and updates the status bits. after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the bank addresses of sectors being suspended should be set when writing the program resume command. the system can determine the program operation status using the dq 7 or dq 6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits from the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the program resume command (address bits are bank address) to exit from the program suspend mode and continue programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device resumes programming.
mbm29xl12df -70/80 41 chip erase command chip erase is a six-bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program prior to erase. upon executing the embedded erase algorithm command sequence the device automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. (preprogram function) the system is not required to provide any controls or timings during these operations. the system can determine the erase operation status by using dq 7 (data polling), or dq 6 (toggle bit). the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see "write operation status" section.) at which the device returns to read the mode. chip erase time: sector erase time all sectors + chip program time (preprogramming) refer to "embedded erase tm algorithm" for typical command strings and bus operations. sector erase command sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever starts later, while the command (data = 30h) is latched on the rising edge of ce or we whichever states first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors are erased concurrently by writing the six bus cycle operations on "mbm29xl12df command definitions table" in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command is not accepted and erasure does not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever starts first initiates the execution of the sector erase command(s). if another falling edge of ce or we , whichever starts first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , "sector erase timer".) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once execution has begun may corrupt the data in the sector. in that case restart the erase on those sectors and allow them to complete. refer to "write operation status" section for sector erase timer operation. loading the sector erase buffer may be done in any sequence and with any number of sectors. sector erase does not require the user to program prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), or dq 6 (toggle bit). the sector erase begins after the t tow time out from the rising edge of ce or we whichever starts first for the last sector erase command pulse and terminates when the data on dq 7 is 1 at which time the device returns to the read mode. see "write operation status" section. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase. in case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. refer to "embedded erase tm algorithm" for typical command strings and bus operations.
mbm29xl12df -70/80 42 erase suspend/resume command the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command is ignored during the chip erase operation. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the addresses are dont cares when writting the erase suspend or erase resume command.when the erase suspend command is written during the sector erase operation, the device takes a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the dq 7 bit is at logic 1, and dq 6 stops toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation is suspended. further writes of the erase suspend command are ignored. when the erase operation is suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode causes dq 2 to toggle. see the section on dq 2 . after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode causes dq 2 to toggle. the end of the erase-suspended program operation is detected by the data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point is ignored. another erase suspend command is written after the chip resumes erasing. fast mode fast mode function dispenses with the initial two unlock cycles required in the standard program command sequence writing fast mode command into the command register. in this mode the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. the read operation is also executed after exiting this mode. during the fast mode, do not write any commands other than the fast program/ fast mode reset command. to exit this mode, write fast mode reset command into the command register. refer to "embedded program algorithm for fast mode". the v cc active current is required even ce = v ih during fast mode. fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). refer to "em- bedded program algorithm for fast mode". query (cfi:common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. this allows device-independent, jedec id-independent, and forward- and backward-compatible software sup- port for the specified flash device families. refer to "common flash memory interface code" in n flexible sector-erase architecture in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 31 to dq 16 ) is 0 in word mode (16 bit) read. to terminate operation, write the read/reset command sequence into the register.
mbm29xl12df -70/80 43 hiddenrom entry command the device has a hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it is protected. however once it is protected, it is impossible to unprotect. therefore extreme caution is required. hiddenrom area is 128 words in bank a. this area is normally the outermost 8k words boot block area. therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. it is called hidden- rom mode when the hiddenrom area appears. the following commands are permitted after issuing the hiddenrom entry command: 1. autoselect 2. password program 3. password verify 4. password unlock 5. read/reset 6. program 7. chip and sector erase 8. hiddenrom protection bit program 9. ppb program 10. all ppb erase 11. ppb lock bit set 12. dpb write 13. dpb/ppb/ppb lock bit verify 14. hiddenrom exit the following commands are unavailable when the hiddenrom is enabled. issuing the following commands while the hiddenrom is enabled results in the command being ignored. 1. cfi 2. set to fast mode 3. fast program 4. reset from fast mode 5. program and sector erase suspend 6. program and sector erase resume the hiddenrom entry command is allowed when the device is in either program or erase suspend modes. if the hiddenrom is enabled, the program or erase suspend command is ignored. this prevents resuming either programming or erase on the hiddenrom if the overlayed sector is undergoing programming or erase. it is the responsibility of the software to resume the program or erase of a suspended program or erase after exiting the hiddenrom. executing any of the ppb program/erase commands, or password unlock command results in the bank a returning the status of these operations while they are in progress, thus making the hiddenrom unavailable for reading. if the hiddenrom is enabled while the dpb command is issued, the dpb for the overlayed sector is not updated. reading the dpb status using the ppb lock bit/dpb verify command when the hiddenrom is enabled returns invalid data.
mbm29xl12df -70/80 44 hiddenrom program command to program the data to the hiddenrom area, write the hiddenrom program command sequence during hid- denrom mode. this command is the same as the program command in usual except to write the command during hiddenrom mode. therefore the detection of completion method is the same as using the dq 7 data polling, and dq 6 toggle bit. need to pay attention to the address to be programmed. if the address other than the hiddenrom area is selected to program, data of the address are changed. hiddenrom protect command the method to protect the hiddenrom is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 1, 1, 1, 0, 1, 0), and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 1, 1, 0, 1, 0) and the sector address in the hiddenrom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 appears on dq 0 if it is not protected. please apply write pulse agian. the same command sequence could be used for the above method because other than the hiddenrom mode, it is the same as the sector protect in the past. and the device has also hiddenrom protect command without v id . see "mbm29xl12df command definitions ta b l e " i n n device bus operation. other sector will be effected if the address other than those for hiddenrom area is selected for the sector address, so please be carefull. once it is protected, protection can not be cancelled, so please pay the closest attention. another method to protect is to issue hiddenrom protection bit program command. this is able to protect hiddenrom area by command only. password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. in word mode, 4 password program commands (in double word mode. 2 password program commands)are required to program the password. the user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any memory location will return the programming status. once programming is complete, the user must issue a read/reset command to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verification. the password program command is only capable of programming 0s. programming a 1 after a cell is programmed as a 0 results in a time-out by the embedded program algorithm with the cell remaining as a 0. the password is all fs when shipped from the factory. all 64-bit password combinations are valid as a password. password programming is permitted if the hiddenrom is enabled. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will always drive all fs onto the dq data bus. the password verify command is permitted if the hiddenrom is enabled. also, the device will not operate in simultaneous operation when the password verify command is executed. only the password is returned re- gardless of the bank address. the lower two address bits (a 1 :a 0 ) are valid during the password verify. writing the read/reset command returns the device back to normal operation.
mbm29xl12df -70/80 45 password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erase. if the password protection mode locking bit is verified as program without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the persistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. the password protection mode locking bit program command is permitted if the hiddenrom is enabled. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the password mode locking bit from ever being programmed. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program command should be reissued to improve program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. the persistent sector protection mode locking bit program command is permitted if the hiddenrom is enabled. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear or the password unlock command is executed. upon setting the ppb lock bit, the ppbs are latched into the dpbs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the read/reset command. the ppb lock bit set command is permitted if the hiddenrom is enabled. dpb write(erase) command the dpb write command is used to set or clear a dpb for a given sector. the high order address bits (a 21 to a 11 ) are issued at the same time as the code 01h or 00h on dq 7 to dq 0 . all other dq data bus pins are ignored during the data write cycle. the dpbs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dpbs are cleared at power-up or hardware reset.exiting the dpb write command is accomplished by writing the read/reset command. the dpb write command is permitted if the hiddenrom is enabled. dpb /ppb verify command dpb/ppb verify command is uesed to verify the status of several sectors. scanning the sector addresses (sa) will produce a logical "1" at the device output dq 0 for a protected sector. otherwise the device will produce "0" at dq 0 for the sector which is not protected. the dpb/ppb verify erify command is permitted if the hiddenrom is enabled. ppb lock bit verify command ppb lock bit verify command is used to verify the status of a ppb lock bit. a logical "1" at the device output dq 1 indicates that the ppb lock bit is set. if ppb lock bit is not set, dq 1 will output"0".the ppb lock bit verify command is permitted if the hiddenrom is enabled.
mbm29xl12df -70/80 46 password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become accessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 m s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 m s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accomplished by writing password unlock command and data to the device to perform the clearing of the ppb lock bit. a 0 and a 1 are used to determine the 16 bit data quantity is used to match separated 16 bits. writing the password unlock command is address order specific. in other words, the lowers address a 1 :a 0 = 00, the next cycle command is to a 1 :a 0 = 01, then to a 1 :a 0 = 10, and finally to a 1 :a 0 = 11. writing out of sequence results in the password unlock not returning a match with the password and the ppb lock bit remains set. once the password unlock command is entered, the ry/by pin goes low indicating that the device is busy. also, reading the bank a results in the dq6 pin toggling, indicating that the password unlock function is in progress. reading the other bank returns actual array data. approximately 1s is required for each portion of the unlock. once the first portion of the password unlock completes (ry/by is not driven and dq 6 does not toggle when read), the next cycle is issued, only this time with the next part of the password. seven cycles password unlock commands are required to successfully clear the ppb lock bit. as with the first password unlock command, the ry/by signal goes low and reading the device results in the dq 6 pin toggling on successive read operations until complete. it is the responsibility of the microprocessor to keep track of the number of password unlock cycles, the order, and when to read the ppb lock bit to confirm successful password unlock. the password unlock command is permitted if the hiddenrom is enabled. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the specific sector address (a 21 to a 11 ) are written at the same time as the program command 60h with a 6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the program command should be reissued to improve the program margin. the ppb program command is permitted if the hiddenrom is enabled. the ppb program command does not follow the embedded program algorithm. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb program, no specific sector address is required. however, when the ppb erase command is written (60h) and a 6 = 1, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased with-out margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. the all ppb erase command is permitted if the hiddenrom is enabled.
mbm29xl12df -70/80 47 write operation status detailed in hardware sequence flags are all the status flags which can determine the status of the bank for the current mode operation. the read operation from the bank which doesnt operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether an embedded algorithm is properly completed. the information on dq 2 is address-sensitive. this means that if an address from an erasing sector is consecutively read, the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows users to determine which sectors are in erase and which are not. the status flag is not output from banks (non-busy banks) which do not execute embedded algorithms. for example, a bank (busy bank) is executing an embedded algorithm. when the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the dq 6 toggles in the case of [1] and [3]. in case of [2], the data of memory cells are output. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in [1] and [3]. hardware sequence flags *1: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2: reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. notes: dq 0 and dq 1 are reserve pins for future use. dq 4 is limited to fujitsu internal use. dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in data polling algorithm. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* 1 erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* 2 program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29xl12df -70/80 48 for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. data polling must be performed at sector addresses of sectors being erased, not pro- tected sectors. otherwise the status may become invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant, and then that bytes valid data at the next instant. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may still be invalid. the valid data on dq 0 to dq 7 will be read on successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. see toggle bit status and data polling during embedded algorithm operation timing diagram. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the busy bank will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequences. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, the device will erase all selected sectors except for protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress) , dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see ac wavefrom for toggle bit i during embedded algorithm operations. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce 1. this is a failure condition indicating that the program or erase cycle was not successfully completed. data polling is only operating function of the device under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in "mbm29xl12df user bus operations table (dw/w = v il )" and "mbm29xl12df user bus operations table (dw/w = v ih )" in n device bus operation.
mbm29xl12df -70/80 49 the dq 5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads valid data on dq 7 bit and dq 6 never stop toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset device with the command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence, sector erase time-out begins. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates that a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun. if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also toggle bit status and "dq 2 vs dq 6 ". furthermore dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system
mbm29xl12df -70/80 50 tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to toggle bit algorithm. toggle bit status * : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by (ready/busy pin) the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or have been completed. if output is low, the device is busy with either a program or erase operation. if output is high, the device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during reset pulse. refer to the following detailed timing diagrams. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up device automatically resets internal state machine to read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequence. device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min). if the embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) can not be used. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle * erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 *
mbm29xl12df -70/80 51 n absolute maximum ratings *1 : voltage is defined on the basis of v ss =gnd=0v. *2 : minimum dc voltage on input or l/o pins is C0.5 v. during voltage transitions, inputs or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc +0.5 v. during voltage transitions,inputs may overshoot to v cc +2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe , reset and acc pins is C0.5 v. during voltage transitions, a 9 , oe , reset and acc pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in C v cc ) does not exceed +9.0 v. maximum dc input voltage on a 9 , oe , reset and acc pins is +13.0 v which may overshoot to +14.0v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss =gnd=0v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground. all pins except a 9 , oe , reset and acc * 1, * 2 v in , v out C0.5 v cc +0.5 v power supply voltage * 1, * 2 v cc C0.5 +4.0 v a 9 , oe , reset and acc * 1, * 3 v in C0.5 +13.0 v parameter symbol part no. value unit min max ambient temperature t a MBM29XL12DF-70/80 C40 +85 c power supply voltage * v cc MBM29XL12DF-70 +3.0 +3.6 v mbm29xl12df-80 +2.7 +3.1 v
mbm29xl12df -70/80 52 n maximum overshoot / maximum undershoot maximum undershoot waveform +0.8 v C0.5 v 20 ns C2.0 v 20 ns 20 ns maximum overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note: this waveform is applied for a 9 , oe , reset , and acc.
mbm29xl12df -70/80 53 n dc characteristics (continued) parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max C1.0 +1.0 a output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 +1.0 a a 9 , oe , reset , acc inputs leakage current i lit v cc = v cc max, a 9 , oe , reset, acc= 12.5v 35 a acc accelerated program cur- rent i lia v cc = v cc max, acc = v acc max 20ma v cc active current * 1 (initial/random read) i cc1 ce = v il , oe = v ih f = 10mhz 70ma ce = v il , oe = v ih f = 5mhz 35ma v cc active current * 2 i cc2 ce = v il , oe = v ih 35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset =v cc 0.3 v, wp = v cc 0.3 v 1 5a v cc current (standby,reset) i cc4 v cc = v cc max, reset =v ssq 0.3 v 1 5a v cc current (page mode) * 3 i cc5 ce = v il , oe = v ih , f = 40mhz 15ma v cc current (automatic sleep mode) * 4 i cc6 v cc = v cc max, ce = v ss 0.3 v, reset =v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 1 5a v cc active current* 6 (read-while-program) i cc7 ce = v il , oe = v ih 50ma v cc active current* 6 (read-while-erase) i cc8 ce = v il , oe = v ih 50ma v cc active current* 6 (erase-suspend-program) i cc9 ce = v il , oe = v ih 35ma
mbm29xl12df -70/80 54 (continued) *1 : l cc current listed includes both the dc operating current and the frequency dependent component. *2 : l cc active while embedded algorithm (program or erase) is in progress. *3 : addresses except a 1 , a 0 , (a -1 ) are fixed. *4 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *5 : about v ih min , it should be applied larger voltage. *6 : embedded algorithm (program or erase) is in progress.(@5 mhz) *7 : v id is only for sector group protection operation and autoselect mode. parameter symbol conditions value unit min typ max input low voltage v il - 0.5 0.6 v input high voltage *5 v ih v cc - 0.2 v cc + 0.3 v voltage for auteselect and sector protection(a 9 , oe, reset )* 7 v id 11.5 12.0 12.5 v voltage for acc program acceleration v acc 11.5 12.0 12.5 v output low voltage v ol i ol = 4.0 ma, v cc = v cc min 0.45 v output high voltage v oh1 i oh = C2.0 ma, v cc = v cc min v cc - 0.4 v v oh2 i oh = C100 a, v cc = v cc min v cc - 0.2 v low v cc lock-out voltage v lko 2.32.42.5v
mbm29xl12df -70/80 55 n ac characteristics ? read only operations characteristics * : test conditions : output load: v cc = 2.7 v to 3.1 v :1 ttl gate and 30pf (MBM29XL12DF-70/80) input rise and fall times: 5 ns input pulse levels: 0.0 v or v cc timing measurement reference level input: 0.5 v cc output: 0.5 v cc parameter symbol condition value * unit 70 80 jedec standard min max min max read cycle time t avav t rc 7080ns address to output delay t avqv t acc ce = v il oe = v il 7080ns page read cycle time t prc 2530ns page address to output delay t pacc ce = v il oe = v il 2530ns chip enable to output delay t elqv t ce oe = v il 7080ns output enable to output delay t glqv t oe 2530ns chip enable to output high-z t ehqz t df 2530ns output enable to output high-z t ghqz t df 2530ns output hold time from address, ce or oe , whichever occurs first t axqx t oh 45ns reset pin low to read mode t ready 2020ns
mbm29xl12df -70/80 56 ? write (erase/program) operations (continued) parameter symbol value unit 70 80 jedec standard min typ max min typ max write cycle time t avav t wc 70 80 ns address setup time t avwl t as 00ns address setup time to oe low during toggle bit polling t aso 12 12 ns address hold time t wlax t ah 45 45 ns address hold time from ce or oe high during toggle bit polling t aht 00ns data setup time t dvwh t ds 35 45 ns data hold time t whdx t dh 00ns output en- able hold time read t oeh 00ns toggle and data polling 10 10 ns ce high during toggle bit polling t ceph 20 20 ns oe high during toggle bit polling t oeph 20 20 ns read recover time before write t ghwl t ghwl 00ns read recover time before write t ghel t ghel 00ns ce setup time t elwl t cs 00ns we setup time t wlel t ws 00ns ce hold time t wheh t ch 00ns we hold time t ehwh t wh 00ns write pulse width t wlwh t wp 35 35 ns ce pulse width t eleh t cp 35 35 ns write pulse width high t whwl t wph 30 30 ns ce pulse width high t ehel t cph 30 30 ns program- ming opera- tion double word t whwh1 t whwh1 1212 s word 6 6 sector erase operation* 1 t whwh2 t whwh2 0.5 0.5 s v cc setup time t vcs 50 50 s rise time to v id * 2 t vidr 500 500 ns rise time to v acc * 3 t vaccr 500 500 ns voltage transition time * 2 t vlht 44s write pulse width* 2 t wpp 100 100 s oe setup time to we active* 2 t oesp 44s ce setup time to we active* 2 t csp 44s
mbm29xl12df -70/80 57 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector group protection operation. *3 : this timing is limited for accelerated program operation only. parameter symbol value unit 70 80 jedec standard min typ max min typ max recover time from ry/by t rb 00ns reset pulse width t rp 500 500 ns reset high level period before read t rh 200 200 ns program/erase valid to ry/by delay t busy 90 90 ns delay time from embedded output enable t eoe 70 80 ns erase time-out time t tow 50 50 s erase suspend transition time t spd 20 20 s dw/w switching low to output high-z t flqz 30 30 ns dw/w switching high to output active t fhqv 70 80 ns
mbm29xl12df -70/80 58 n erase and programming performance notes : typical erase conditions: t a = + 25c, v cc = 2.9 v typical program conditions: t a = + 25c, v cc = 2.9 v, data = checker n ssop pin capacitance notes : test conditions: t a = + 25c, f = 1.0 mhz dq 31 /a -1 pin capacitance is stipulated by output capacitance. n fbga pin capacitance note : test conditions: t a = + 25c, f = 1.0 mhz dq 31 /a -1 pin capacitance is stipulated by output capacitance. parameter value unit comments min typ max sector erase time 0.5 2 s excludes programming time prior to erase double word programming time 12 150 s excludes system-level overhead word programming time 6 100 chip programming time 50.3 200 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol test setup value unit typ max input capacitance c in v in = 0 7.0 10.0 pf output capacitance c out v out = 0 6.0 12.0 pf control pin capacitance c in2 v in = 0 7.5 11.0 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 tbd tbd pf output capacitance c out v out = 0 tbd tbd pf control pin capacitance c in2 v in = 0 tbd tbd pf
mbm29xl12df -70/80 59 n timing diagram ? key to switching waveforms read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h h or l: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance off state we oe ce t df t ce t oe outputs address address stable high-z output valid high-z t oeh t acc t rc t oh
mbm29xl12df -70/80 60 a 1 to a 0 (a -1 ) ce oe we outputs high-z a 21 to a 2 same page address t rc t prc t prc t acc t ce t oe t oh t pacc t df t oeh aa ab ac ad t oh t pacc t oh t oh t pacc da db dc dd page read operation timing diagram hardware reset/read operation timing diagram address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh
mbm29xl12df -70/80 61 ry/by timing diagram during program/erase operation timing diagram ce ry/by we rising edge of the last we signal t busy entire program or erase operations reset , ry/by timing diagram t rp t rb t ready ry/by we reset
mbm29xl12df -70/80 62 notes: pa is address of the memory location to be programmed. pd is data to be programmed at word address (x16 mode). dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 32 mode. (the addresses differ from 16 mode.) alternate we controlled program operation timing diagram t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df
mbm29xl12df -70/80 63 alternate ce controlled program operation timing diagram notes: pa is address of the memory location to be programmed. pd is data to be programmed at word address (x16 mode). dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 32 mode. (the addresses differ from 16 mode.) t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd
mbm29xl12df -70/80 64 chip/sector erase operation timing diagram * : sa is the sector address for sector erase. address = 555h (double word). aaah (word) for chip erase. v cc ce oe address data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 10h for chip erase 30h note : these waveforms are for the 32 mode. (the addresses differ from 16 mode.)
mbm29xl12df -70/80 65 t oeh t oe t whwh1 or 2 ce oe t eoe we data t df t ch t ce high-z high-z dq 7 = valid data dq 6 to dq 0 valid data dq 7 * dq 7 dq 6 to dq 0 data dq 6 to dq 0 = output flag data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation.)
mbm29xl12df -70/80 66 ac waveforms for toggle bit i during embedded algorithm operations *: dq 6 stops toggling (the device has completed the embedded operation.) t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph
mbm29xl12df -70/80 67 bank-to-bank read / write(program and erase) timing diagram ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2 dq 2 vs. dq 6 enter embedded erase erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 * we toggle dq 2 and dq 6 with oe or ce * : dq 2 is read from the erase-suspended sector.
mbm29xl12df -70/80 68 double word mode configuration timing diagram ce dw/w t elfh t fhqv a -1 data output (dq 15 to dq 0 ) dq 31 dq 31 /a -1 dq 30 to dq 0 (dq 30 to dq 0 ) data output t ce word mode configuration timing diagram ce dw/w dq 31 /a -1 dq 30 to dq 0 t elfl dq 31 a -1 t flqz data output (dq 15 to dq 0 ) (dq 30 to dq 0 ) data output t acc falling edge of the last write signal t hold ce or we (t ah ) t set (t as ) input valid dw/w dw/w timing diagram for write operations
mbm29xl12df -70/80 69 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht address (a 21 to a 11 ) a 6 , a 2 , a 0 a 5 , a 4 , a 3 , a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay spax : sector group address to be protected spay : next sector group address to be protected note : a -1 is v il in word mode. sector group protection timing diagram
mbm29xl12df -70/80 70 temporary sector group unprotection timing diagram unprotection period t vlht t vlht t vcs t vlht t vidr program command sequence v cc v id v ih we ry/by ce reset
mbm29xl12df -70/80 71 extended sector group protection timing diagram sgax : sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min) v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out sgax sgax sgay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 2 , a 0 a 5 , a 4 , a 3 , a 1 v id v ih
mbm29xl12df -70/80 72 acc v cc ce we t vlht program command sequence t vlht t vcs t vaccr v acc t vlht acceleration period v ih accelerated program timing diagram
mbm29xl12df -70/80 73 embedded program tm algorithm no yes start program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address verify data ? program address/program data programming completed last address ? yes no embedded algorithm embedded program algorithm in progress notes : the sequence is applied for 32 mode. the addresses differ from 16 mode.
mbm29xl12df -70/80 74 embedded erase tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequence (see below) data polling or toggle bit from device erasure completed chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h start data = ffh no yes ? embedded algorithm embedded erase algorithm in progress note : the sequence is applied for 32 mode. the addresses differ from 16 mode.
mbm29xl12df -70/80 75 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erase operation. = any of the sector addresses within the sector not being protected during chip erase operation. fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va yes *
mbm29xl12df -70/80 76 no dq 6 = toggle? dq 5 = 1? yes no yes read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start * 1 read dq 7 to dq 0 addr. = va * 1, * 2 dq 6 = toggle? yes no program/erase operation not complete, write reset command program/erase operation complete read dq 7 to dq 0 addr. = va * 1, * 2 * 1 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1. va = bank address being excuted embedded algorithm
mbm29xl12df -70/80 77 setup sector group addr. (a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , ce = v il , reset = v ih a 6 = a 2 = a 0 = v il , a 5 = a 4 = a 3 = a 1 = v ih plscnt = 1 time out 100 m s remove v id from a 9 write reset command increment plscnt no yes protect another sector group ? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector group protection completed read from sector group (addr. = spa, a 6 = a 2 = a 0 = v il , a 5 = a 4 = a 3 = a 1 = v ih ) * sector group protection algorithm * : a -1 is v il in word mode.
mbm29xl12df -70/80 78 temporary sector group unprotection algorithm *1 : all protected sector groups are unprotected. *2 : all previously protected sector groups are reprotected once again. start perform erase or program operation reset = v id *1 reset = v ih temporary sector group unprotection completed *2
mbm29xl12df -70/80 79 extended sector group protection algorithm start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector group protection completed protect other sector group? increment plscnt read from sector group address (addr. = sga, a 6 = a 2 = a 0 = v il , a 5 = a 4 = a 3 = a 1 = v ih )* remove v id from reset write reset command time out 250 m s reset = v id wait to 4 m s no yes setup next sga device is operating in temporary sector group unprotection mode to protect sector group write 60h to sga a 6 = a 2 = a 0 = v il , a 5 = a 4 = a 3 = a 1 = v ih to verify sector group protection write 40h to sga a 6 = a 2 = a 0 = v il , a 5 = a 4 = a 3 = a 1 =v ih to setup sector group protection write xxxh/60h extended sector group protection entry? () ( ) * : a -1 is v il in word mode.
mbm29xl12df -70/80 80 embedded program algorithm for fast mode fast mode algorithm yes no 555h/aah verify data? start 555h/20h 2aah/55h xxxh/a0h program address/program data data polling device last address ? programming completed ba/90h xxxh/f0h increment address yes no set fast mode in fast program reset fast mode
mbm29xl12df -70/80 81 dq 0 = 1? protect another ? no no yes hiddenrom entry hiddenrom exit hiddenrom exit ppb program operation start yes ppb protection completed ppb protection algorithm
mbm29xl12df -70/80 82 protect another ? no hiddenrom entry hiddenrom exit dpb program operation start yes dpb protection algorithm
mbm29xl12df -70/80 83 read auto-select ppb bit status dq 0 = 0 (unprotected) dq 0 = 1 (protected) dq 0 = 0 (unprotected) dq 0 = 1 (protected) note: this output indicates the or between dpb and ppb note: this output indicates ppb lock bit dq 1 = 0 (unprotected) dq 1 = 1 (protected) start hiddenrom entry dpb/ppb & ppb lock bit status command start dpb/ppb ppb lock bit dpb/ppb & ppb lock bit status ppb protection status protection status
mbm29xl12df -70/80 84 hiddenrom entry password verify hiddenrom exit password program operation * start addr. = 555h data = 55h addr. = aaah data = 38h addr. = aaah data = aah addr. = xx0h to xx3h data = pd0 to pd3 repeat 4-times password mode set * : password program (word mode)
mbm29xl12df -70/80 85 password sector protect algorithm password program dq 0 = 0? start password mode choice method reset command password protection correct? no (time out) mode bit program reset command password verify reset command program complete yes yes no
mbm29xl12df -70/80 86 ppb lock bit clear in password mode password unlock ry/by = h? start ppb lock clear in password mode dq 0 = 1? no (time out) reset command program complete yes password unlock dpb/ppb/ppb lock bit status no password/unlock complete reset command all ppb erase dq 0 = 0? yes no (time out) yes
mbm29xl12df -70/80 87 n ordering information mbm29xl12d device number/description mbm29xl12d 128 mega-bit (8m 16-bit or 4m 32-bit) page mode flash memory 3.0 v-only read, program, and erase package type pfv = 90-pin shrink outline l-leaded package (ssop) pbt = 96-ball fine pitch ball grid array package (fbga) part number package access time (ns) remarks mbm29xl12df 70pfv mbm29xl12df 80pfv 90-pin plastic ssop (fpt-90p-m01) 70 80 mbm29xl12df 70pbt mbm29xl12df 80pbt 96-ball plastic fbga (bga-96p-m02) 70 80 70 f pfv speed option see "product selector guide". device revision
mbm29xl12df -70/80 88 n package dimensions (continued) 90-pin plastic ssop (fpt-90p-m01) note 1) *1 : these dimensions include resin protrusion. note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f90001s-c-2-2 1 45 46 90 23.700.30(.933.012) 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) 0.08(.003) 13.300.20 (.524.008) 16.000.30 (.630.012) .007 C.001 +.002 C0.03 +0.05 0.17 .035 C.006 +.005 C0.15 +0.12 0.88 0.550.10 (.022.004) 1.800.10 (.071.004) (mounting height) (stand off) "a" 0.25(.010) 0 ? ~8 ? details of "a" part index * 1 * 2
mbm29xl12df -70/80 89 (continued) 96-ball plastic fbga (bga-96p-m02) dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited b96002s-c-1-1 .041 C .004 +.006 C 0.10 +0.15 1.05 (mounting height) 0.38 0.10 (.015 .004) (stand off) index area a b c d e f g h j k l m n p 11 9 8 7 6 5 4 3 2 1 index side 14.50 0.10(.571 .004) 9.50 0.10 (.374 .004) 0.40(.016) ref 0.80(.031) ref b a r q s b a s m 0.08(.003) 96- ? 0.45 0.05 (96- ? .018 .002) 0.80(.031) ref 0.40(.016) ref 0.10(.004) s 10
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